It is a known fact that stress can vary the band gap and carrier mobility in silicon. Recently, stress has become one of the most important factors affecting a MOS transistor's performance. If the stress could be appropriately controlled, carrier mobility (electron mobility in N-channel transistors and hole mobility in P-channel transistors) may be increased, and thereby enhancing the drive current. Hence, increasing the stress can significantly improve the transistor's performance.
Currently, dual-stress techniques are employed to form tensile stress liners over NMOS transistors and compressive stress liners over PMOS transistors, so that the drive currents of both the PMOS transistors and the NMOS transistors may be increased, which may reduce the circuit response period.
Conventionally, when forming contact holes for a semiconductor device with dual-stress liners, the dual-stress liners need to be etched to expose silicide materials buried thereunder. Over-etch may occur in the etching process, resulting in silicide loss. This may adversely affect the device performance. Therefore, there is a need to provide a method for forming contact holds for a semiconductor device with dual-stress liners, which may suppress over-etch and thus reduce silicide loss.